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Chip Makers Use New Methods to Get More Bang for the Buck by Don Clark, Staff Reporter Wall Street Journal - October 5, 2004

IBM, Rivals Plan to Pack Energy-Efficient Processors on New-Era Semiconductors

Chip makers, facing diminishing returns from a technology-development technique used for decades, are discussing future products this week that take new routes to higher performance.

Product designs being disclosed at a technical conference in Silicon Valley reflect a widening recognition that simply shrinking transistors -- a technique sometimes called scaling -- is becoming less practical to make chips work faster. At current microscopic sizes, transistors increasingly leak so much electrical current that they use the same amount of energy when they are doing nothing as when they are working.

"There is a groundswell of acceptance that you cannot continue classical scaling," says Bernard Meyerson, chief technologist for International Business Machines Corp.'s systems and technology group.

While researchers explore new materials to try to minimize power consumption, chip designers are turning to more-efficient techniques. One big trend is to put the equivalent of two or more microprocessors on a chip, an approach that will show up frequently in presentations at this week's Fall Processor Forum in San Jose, Calif.

IBM, a pioneer in such "multicore" chips, will discuss how it used the approach with BlueGene/L, a supercomputer that the company said last week was the world's most powerful. Where others have built such machines from the fastest components available, IBM designers created chips using two microprocessors that are slimmed-down variants of its PowerPC family and operate at 700 megahertz, less than a third of the speed of some members of that chip family.

But the slimmed-down microprocessors draw about four watts of power, IBM says, compared with 24 watts for typical PowerPC chips. Low power consumption was crucial for IBM to be able to pack 64,000 processors into a system of manageable size, said Alan Gara, the IBM chief architect who led the supercomputer-design effort.

In other conference presentations, Sun Microsystems Inc. will discuss a two-processor chip called UltraSparc IV+ that should double the performance of its fastest chip line next year, said David Yen, executive vice president of Sun's scalable systems group. In 2006, Sun plans to follow up with Niagara, the code name for a chip with eight processors.

Advanced Micro Devices Inc. is also expected to give additional details of a dual-processor chip that it is hoping to deliver next year ahead of rival Intel Corp.

The conference will also focus on new designs for multicore chips aimed at more-specialized applications. Broadcom Corp. says it has developed a four-processor chip that is targeted at communications applications, as well as data storage and security. Cavium Networks Inc., a Santa Clara, Calif., startup, is discussing plans for a specialty networking chip with two to 16 processors on a single piece of silicon.

IBM's Mr. Meyerson, who is speaking at the conference today, stresses that power-consumption problems don't mean that companies will stop the pace of shrinking transistors. But that miniaturization will primarily reduce production costs; to get greater performance, companies will have to enhance all aspects of computer design.

"It opens a whole new era, the era of holistic design," Mr. Meyerson said.